This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to the formation of a silicon nitride film formed over a ferroelectric capacitor structure in an integrated circuit.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic devices and systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example placing capacitors above the transistor level, between overlying levels of metal conductors.
FIG. 1 illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage +Vα, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage −Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the difference in capacitance exhibited by a ferroelectric capacitor between its polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. In the context of a ferroelectric capacitor, the change in polarization state that occurs upon application of a polarizing voltage is reflected in charge storage. For example, referring to FIG. 1, the polarization of a ferroelectric capacitor from its “−1” state to its “+1” state is reflected in a relatively high capacitance C(−1), by way of which polarization charge involved in the change of polarization state is retained within the capacitor as the voltage exceeds its coercive voltage Vα; on the other hand, a capacitor already in its “+1” state exhibits little capacitance C(+1) due to polarization, since its ferroelectric domains are already aligned prior to the application of the voltage. In each case, the ferroelectric capacitor also has a linear capacitance, by virtue of its construction as parallel plates separated by a dielectric film (i.e., the ferroelectric material). As will be evident from the following description, a stored logic state is read by interrogating the capacitance of ferroelectric capacitors to discern its polarized state.
Ferroelectric technology is now utilized in non-volatile solid-state read/write random access memory (RAM) devices. These memory devices, commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, are now commonplace in many electronic systems, particularly portable electronic devices and systems. FeRAMs are especially attractive in implantable medical devices, such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T2C (two transistor, two capacitor) cells. Another type of FeRAM cell is based on the well-known “6T” CMOS static RAM cell, which operates as an SRAM cell during normal operation, but in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state to preserve memory contents in non-volatile fashion. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors.
It has been observed that the properties of conventional ferroelectric capacitors are quite sensitive to the presence of hydrogen. More specifically, the infiltration of hydrogen into the ferroelectric film is believed to cause degradation in the hysteresis characteristic of the ferroelectric capacitor, primarily by inhibiting its programmability into two separate states. FIGS. 2a and 2b illustrate a theory of the mechanism for this degradation as caused by hydrogen in the ferroelectric film.
FIG. 2a illustrates the crystalline structure of PZT ferroelectric material by way of a unit cell having lead atoms 2 at its vertices, and oxygen atoms 4 at the center of each face. Zirconium titanate molecule 5 resides at one of two possible positions in the interior of this unit cell, at each of which it can bond to oxygen atoms 4. Position 6 is empty in the illustration of FIG. 2a, and is the other position in the crystal structure at which oxygen bonds are available to zirconium titanate molecule 5. An electric field applied in parallel with the axis of the two interior positions of the unit cell can move zirconium titanate molecule 5 from one position to the other; it is this change in position of zirconium titanate molecule 5 that causes the hysteresis behavior in the C-V plot, as shown in FIG. 1.
FIG. 2b illustrates this same crystalline structure of PZT ferroelectric material, but in which the crystal has been contaminated by hydrogen atom 6H. As shown in FIG. 2b, hydrogen atom 6H occupies bonds to oxygen atoms 4 at one of the two interior positions of the crystal unit cell. With those available bonds now occupied, zirconium titanate molecule 5 cannot readily change its position within the PZT crystal in response to an applied electric field. The hysteresis characteristic of the ferroelectric capacitor will thus collapse to the extent that cells of the crystal structure of the ferroelectric material are hydrogen-contaminated in the manner shown in FIG. 2b. 
Conventional process flows for manufacturing ferroelectric capacitors have addressed the issue of hydrogen contamination of the ferroelectric material by depositing passivation films over the ferroelectric capacitor structure. FIG. 3 is a cross-sectional view of a ferroelectric capacitor structure within an integrated circuit, constructed according to an example of such a conventional fabrication method. In the structure of FIG. 3, an n-channel MOS transistor is realized at the surface of p-type substrate 10 (or well), at an active region disposed between isolation dielectric structures 15 (formed by shallow trench isolation in this example). N+ source/drain regions 14 are formed into substrate 10 on opposing sides of polysilicon gate element 16 in a self-aligned manner. Gate element 16 is separated from the surface of the active region by gate dielectric 17, thus forming the MOS transistor. Sidewall spacers 19 are provided on the sides of gate element 16 as useful in forming source/drain region extensions, as known in the art. A ferroelectric capacitor is formed by a ferroelectric stack including conductive plates 20a, 20b (formed of an elemental metal, or a conductive metal compound such as a nitride or silicide, or a stack of two or more of these layers) between which ferroelectric material 22 is disposed. In this example, ferroelectric material 22 consists of PZT. Typically, as known in the ferroelectric integrated circuit art, this ferroelectric stack is formed by the sequential deposition of the conductive and ferroelectric materials, etched to the desired dimensions by a single stack etch. Bottom conductive plate 20a is connected to the source/drain region 14 by conductive plug 18 formed into a contact opening etched through dielectric film 13.
To inhibit hydrogen contamination of ferroelectric material 22, multiple passivation films are formed over the ferroelectric stack as shown in FIG. 3. In this conventional example, aluminum oxide layer 24 is first formed over the ferroelectric stack by conventional chemical vapor deposition or atomic layer deposition, for example to a thickness of about 25 nm. This aluminum oxide layer 24 is quite conformal to the non-planar structure of the ferroelectric stack, serves as a hydrogen barrier, and also as a chemical barrier between ferroelectric material 22 and the other passivation films.
Silicon nitride layer 25 is then formed over aluminum oxide layer 24 in this conventional arrangement, for example to a thickness of about 50 nm, by high-density plasma (HDP) chemical vapor deposition (CVD). As known in the art, HDP CVD is a specific type of plasma-enhanced chemical vapor deposition (PECVD) in which an inductively-coupled plasma (ICP) creates a high-density plasma in the processing reactor, in contrast to parallel-plate plasma reactors in which energy is capacitively coupled to the plasma. Yota et al., “A comparative study on inductively-coupled plasma high-density plasma, plasma-enhanced, and low pressure chemical vapor deposition silicon nitride films” J. Vac. Sci. Technol. A, 18(2) (American Vacuum Society, March/April 2000), pp. 372-76, describes a process for depositing CVD silicon nitride by way of HDP techniques, in which the gas species provided to the HDP reactor are SiH4 and N2, with argon as a dilution gas. In contrast, the conventional PECVD silicon nitride film described in this article uses gas species of SiH4 and NH3, with N2 as the dilution gas, all of which are injected into a parallel plate plasma reactor. The Yota et al. article further describes that the HDP silicon nitride film contains less hydrogen than does the conventional PECVD film. In addition, the hydrogen contained in the HDP nitride film is present in the form of N—H bonds, rather than as Si—H; the Yota et al. article asserts that the hydrogen from Si—H bonds is more easily broken than that from N—H bonds.
As shown in FIG. 3, another silicon nitride film 26 overlies HDP nitride film 25. This top silicon nitride film is commonly in the form of “UV nitride”, which refers to a silicon nitride film that is transmissive to ultraviolet light. UV nitride is typically deposited by way of conventional PECVD in a parallel-plate reactor, with SiH4 and NH3 as the source gases and N2 as a dilution gas. U.S. Pat. No. 6,924,241 describes a process in which a low concentration of NH3 source gas is used in the PECVD of UV transmissive nitride, to improve the UV transmittance of the film. In the conventional example of FIG. 3, UV nitride 26 is deposited to a thickness (e.g., about 50 nm) sufficient to fill any gaps or thin spots (i.e., voids) in HDP nitride 25, and to increase the thickness of the overall passivation layer, considering that the step coverage of HDP nitride film 25 is typically quite poor.
However, the use of HDP CVD to form the first nitride layer (nitride film 25 in FIG. 3) is a costly and complicating process step in the overall manufacturing flow of the integrated circuit including the ferroelectric capacitor. As known by those in the industry, HDP (i.e., inductively-coupled plasma) reactors are relatively expensive. Manufacturing process flows thus avoid HDP CVD to the extent possible. If HDP CVD is required for a specific purpose, use of the HDP reactor is generally limited to those specific processes, to minimize the cost of adding additional HDP capacity. Even so, the insertion of an HDP CVD process into the manufacturing flow can result in bottlenecks, and limits the extent to which multiple processes are performed in situ in a single reactor.